A failure of a semiconductor device may occur in one of an initial failure period, a chance failure period, and a wear failure period. These periods are determined according to a period of time from a start of use of the semiconductor device. In the initial failure period immediately after the use of the semiconductor device, an initial failure may frequently occur. In the chance failure period after an occurrence rate of the initial failure has reached a certain level and then has been stabilized, a failure may occur due to an accidental cause. In the wear failure period, a wear failure may frequently occur due to the end of the life of the semiconductor device as a product after the semiconductor device has continued to be used for a long period to time. It is known that, when failure occurrence rate is plotted along a vertical axis and time is plotted along a horizontal axis to create a graph, a so-called bathtub curve is obtained. That is, it can be seen that the failure occurrence rate is high in the initial failure period, the failure occurrence rate decreases in the chance failure period, and the failure occurrence rate increases again in the wear failure period.
Accordingly, when an initial failure is removed by screening before the start of use of the semiconductor device in order to reduce the failure occurrence rate of the semiconductor device, the failure occurrence rate can be reduced until the wear failure period starts. Burn-in is performed in a final production procedure of a semiconductor product, as a step of removing an initial failure by screening. This burn-in is a semiconductor device final production step where a semiconductor device, which has been initially determined to be a good product in a selection procedure of semiconductor devices, is operated in a state that is close to an actual use operation of the semiconductor device as much as possible under an environment of high power supply voltage and high temperature, thereby performing screening and aging. By performing a selection test again after this burn-in, the initial failure is removed. A final product not including the initial failure can be thereby shipped.
The burn-in is performed under the environment of high power supply voltage and high temperature in order to accelerate the screening. The higher a power supply voltage and a temperature are, the more effective it is to accelerate the screening. On the other hand, when the power supply voltage and the temperature are too high, the semiconductor device may be broken. Accordingly, the burn-in of the semiconductor device is performed under the environment of the power supply voltage and the temperature that are high as much as possible within a range that will not destroy the semiconductor device.
It is known that power consumption of the semiconductor device during burn-in may increase more than under a normal use condition of the semiconductor device because the burn-in is performed at high power supply voltage and at high temperature, as mentioned above. Patent Document 1 describes a semiconductor memory device (DRAM) capable of reducing power consumption that may increase during this burn-in. Patent Document 1 describes reduction of leak current in PMOS and NMOS transistors used for a sense amplifier differential circuit when the PMOS and NMOS transistors are turned off, during burn-in. Reduction of leak current is achieved by setting a substrate voltage of the PMOS transistor to be higher during the burn-in than during a normal operation and setting a substrate voltage of the NMOS transistor to be lower during the burn-in than during the normal operation. Patent Document 1 does not describe reduction of current consumption in the step of burn-in when the differential circuit is in an operation state.
Patent Document 2 describes a differential type input initial stage circuit that fetches a command/address supplied through an external terminal at high speed in a semiconductor memory device in compliance with DDR specifications, though not directly related to burn-in.    [Patent Document 1]    JP Patent Kokai Publication No. JP2004-2297710A, which corresponds to U.S. Pat. No. 6,903,976    [Patent Document 2]    JP Patent Kokai Publication No. JP2009-104694A